1. Field of the Invention
This invention relates to the field of phase-locked loop (PLL) circuits, and particularly to PLL circuits used to distribute multiple clock signals.
2. Description of the Related Art
Most digital electronic circuits operate in response to a clock signal. In some applications, a number of different integrated circuits (ICs) each require their own clock signal, with all the clock signals derived from and in phase with a reference clock.
One method of accomplishing this is with the use of a phase-locked loop (PLL) circuit, which receives a reference clock and produces an output signal which is in-phase with the reference clock. A conventional PLL circuit is shown in FIG. 1. Here, a reference clock 10 having a frequency fref is applied to one input of a phase detector 11, which also receives a second input 12. The phase detector produces an output 14 which varies with the phase difference between its two input signals. Output 14 is provided to a loop filter 16, the output of which is applied to the control input 18 of a voltage-controlled oscillator (VCO) 20. The VCO produces an output 22 having a frequency fVCO which is applied to the input of a divide-by-N circuit 24. The output 26 of divider 24 has a frequency fdiv, and is fed back to input 12 of phase detector 10.
In operation, N is typically a fixed integer. The frequency fVCO is N times higher than fref, and is divided down to fref by divider 24. When the loop is “locked”, the voltage applied by loop filter 16 to VCO input 18 drives the phase difference between phase detector input signals 10 and 12 to zero, such that output 26—CLK OUT—has a frequency fdiv which is equal to fref, and which is in phase with fref.
VCO 20 is conventionally made from a ring oscillator, as illustrated in FIG. 1. Ring oscillators have a wide output frequency range; as such, they are well-suited for use in PLL circuits which lock to a reference clock that can have several different frequencies. For example, the frequency fref of reference clock 10 might switch between frequencies of 100 MHz, 200 MHz, and 400 MHz. If N is a fixed integer, the VCO output needs to have a wide frequency range if the PLL is to be capable of locking onto each of these reference clocks.
One drawback to the use of a ring oscillator-based VCO is its relatively high jitter specification. In some applications, clock jitter is required to be less than a particular value. For example, for a particular type of DRAM known as DDR DRAM, the Joint Electron Device Engineering Council (JEDEC) has established limits for certain parameters associated with DDR DRAM—including the amount of jitter which may be present in the clock signals fed to the DDR DRAM chips. The clock signals generated with some PLL circuits, such as ones employing a ring oscillator-based VCO, may exceed the JEDEC specification.